Miniaturization of consumer electronics with increased functionality and high density memory has long been one of the major drivers in semiconductor packaging developments. Extremely dense electronics can be created by stacking thin silicon chips with interconnections in the vertical direction. Through silicon via (TSV) process is one of the techniques used in the packaging industry which enables stacking of thin silicon integrated circuits (ICs) to provide heterogeneous integration and a potential increase in the physical density of some electronic systems' functions. Additionally, this technology enables potential architectural configurations for true vertical integration among multiple IC layers by dramatically increasing the area interconnect capability of a given IC.
It is desirable to improve on TSV technology, for example, simplifying design and processing to improve yields, decrease costs and/or improving throughput.